This invention relates to the fabrication of semiconductor integrated circuits ICs). More particularly, the present invention relates to methods and apparatus for efficiently removing photoresist mask defects on a substrate and/or etching through an organic-based antireflective coating layer.
In semiconductor fabrication, devices such as component transistors may be formed on a substrate, e.g., a semiconductor wafer or a glass panel. Above the substrate, there may be disposed a plurality of layers from which the devices may be fabricated. Metallic interconnect lines, which may be etched from a metal layer disposed above the substrate, may then be employed to couple the devices together to form the desired circuit. To facilitate discussion, FIG. 1 illustrates a cross-sectional view of a layer stack 20, representing the layers of an exemplar semiconductor IC. In the discussions that follow, terms such as "above" and "below," which may be employed herein to discuss the spatial relationship among the layers, may, but need not always, denote a direct contact between the layers involved. It should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of layer stack 20, there is shown a substrate 100. An oxide layer 102, typically comprising SiO.sub.2, may be formed above substrate 100. A barrier layer 104, typically formed of a titanium-containing layer such as Ti, TiW, TiN or other suitable barrier materials, may be disposed between oxide layer 102 and a subsequently deposited metal layer 106. Barrier layer 104, when provided, may function to prevent the diffusion of silicon atoms from oxide layer 102 into the metal layer. Metal layer 106 typically comprises, for example, copper, aluminum or one of the known aluminum alloys such as Al--Cu, Al--Si or Al--Cu--Si.
The remaining layers of FIG. 1, i.e., an antireflective coating (ARC) layers 108 and 110 and an overlaying photoresist (PR) layer 112, may then be formed atop metal layer 106. The ARC layer 108, typically comprising another titanium-containing layer such as Ti, TiN or TiW, may help prevent light (e.g., from the lithography step that patterns the photoresist) from being reflected and scattered off the surface of the metal layer 106 and may, in some cases, inhibit hillock growth. For some substrates, e.g., those being scaled with narrow design rules such as 0.25 microns or below, layer stack 20 may further include an optional layer of organic-based antireflective material (e.g., polyamide-based antireflective material), which is typically disposed above the layer of conventional (e.g., Ti, TiN, or TiW) antireflective material. The optional organic-based antireflective material is depicted in FIG. 1 as organic ARC layer 110.
Photoresist layer 112 represents a layer of conventional photoresist material, which may be patterned for etching, e.g., through exposure to ultra-violet rays. The layers of layer stack 20 are readily recognizable to those skilled in the art and may be formed using any of a number of suitable and known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) such as sputtering.
To form the aforementioned metallic interconnect lines, a portion of the layers of the layer stack, including the metal layer, e.g., metal layer 106, is etched using a suitable photoresist technique. By way of example, one such photoresist technique involves the patterning of photoresist layer 112 by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. Using appropriate etchants, the areas of the metal layer that are unprotected by the mask may then be etched away, leaving behind metal interconnect lines or features. For illustration purposes, FIG. 2 shows a somewhat idealized cross-sectional view of layer stack 20 of FIG. 1 after the main etching step, i.e., metal etching, is completed. In this example, feature 202, representing the unetched portion through layers 110, 108, 106, and 104, forms an interconnect line on substrate 100.
To achieve greater circuit density, modern IC circuits are scaled with increasingly narrower design rules. As a result, the feature sizes, i.e., the width of the interconnect lines or the spacings (e.g., trenches) between adjacent interconnect lines, have steadily decreased. By way of example, while a line width of approximately 0.8 microns (.mu.m) may be considered acceptable in a 4 megabit (Mb) dynamic random access memory (DRAM) IC, 256 Mb DRAM IC's preferably employ interconnect lines as thin as 0.25 microns or even thinner.
As the feature sizes shrink, it becomes increasingly difficult to achieve a defect-free photoresist mask for etching the underlying layers of the substrate layer stack. By way of example, as the critical dimension (i.e., width) of the photoresist mask features shrinks, it may not be possible to remove all the photoresist material in areas where photoresist material is undesired, i.e., in the trenches of the photoresist mask. The remaining layers or blocks of unwanted photoresist material at the bottom of the trenches of the photoresist mask represent defects in the photoresist mask since they affect subsequent etching processes.
By way of example, FIG. 3 illustrates an example of a layer stack 300 whose photoresist mask suffers from defects. In FIG. 3, layers 100, 102, 104, 106, 108, and 110 are substantially similar to layers having like reference numerals in FIG. 1. Photoresist mask 112 which has been processed in accordance with a conventional photoresist process, suffers from scumming layer-type defect in trench 302 and sloped foot-type defect in trench 304.
The scumming layer-type defect may be caused by the incomplete removal of the photoresist material in trench 302 such that a thin layer of photoresist remains at the bottom of the trench. Scumming layer-type defects, which may frequently occur in narrow (e.g., below 0.35 micron wide) and high aspect ratio (e.g., above 3:1) trenches, affect, among others, the uniformity of the subsequent etch process (e.g., metal etch) since the underlying layers in trench 302 are undesirably shielded from the subsequent etch step. In severe cases, there may be a loss of control of over the critical dimension of the mask since the subsequent etch step may need to be extended to clear the defects, to the detriment of the protective mask features.
The sloped foot-type defect may also be caused by the incomplete removal of photoresist material in trench 304 such that there exists a sloped foot attached to the bottom of the photoresist mask feature. Sloped foot-type defects may result in, for example, a change in the critical dimension of the etched feature (e.g., the width d1 of feature 202 in the example of FIG. 2) since the blocks of unwanted photoresist material may exert a "shadowing" or shielding effect to modify the evolution of the etch profile, e.g., narrowing the underlying etched feature. Further, this may also affect microloading and/or aspect ratio dependent etching issues. Changes in the critical dimension may result in reduced circuit yield since, for example, the critical dimension of the resultant etched feature may be unduly narrow, leading to its failure in manufacturing or in use (e.g., when current is applied).
In the prior art, photoresist mask defects are remedied by performing either an ash-type process or a bombardment-type process on the photoresist mask. Bombardment-type processes subject the substrate to physical bombardment by the etchant species. In one example, bombardment is performed in a transformer-coupled plasma processing chamber. At high bottom electrode power, the etchant species are accelerated toward the surface of the substrate to essentially sputter away the defect. Bombardment may also be increased by, for example, increasing the flow of etchant and/or reducing the chamber pressure. There are, however, disadvantages associated with bombardment-type processes. For example, it is recognized that bombardment-type processes may erode away the desirable photoresist mask features at the same time it erodes away the unwanted photoresist material, e.g., the scumming layer or the sloped foot of FIG. 3. Accordingly, bombardment-type processes tend to unduly reduce the ability of the photoresist mask, after bombardment, to protect the underlying layers from undesirable etching in subsequent etching steps.
Ash-type processes subject the substrate to oxidant-based chemistries, i.e., those containing O.sub.2, which react with and erodes away photoresist. There are, however, disadvantages associated with ash-type processes as well. For example, it is recognized that ash-type processes may also erode away the desirable photoresist mask features at the same time they erode away the unwanted photoresist material, thereby reducing the ability of the photoresist mask, after ashing, to protect the underlying layers from undesirable etching in subsequent etching steps.
Ash-type processes are also typically performed in a reactor module that is different from the module employed for metal etching. This is because the oxygen-based chemistries of the ash process, if employed in the metal etch reactor, may react with certain chemistries typically employed for metal etching, e.g., BCl.sub.3, and form an undue amount of polymer particles in the reactor chamber. In addition to increasing particle contamination, the increase in the amount of formed polymer particles also necessitates more frequent cleaning of the chamber, which increases cost. The use of a different reactor chamber to perform ash-type processes also introduces one or more additional steps into the fabrication process, thereby increasing the amount of time required to process a substrate, and reducing substrate throughput. For example, after a substrate has been processed via a conventional photoresist process, it may be necessary to employ a separate chamber to perform an ash-type process on the substrate to remedy photoresist mask defects, remove the substrate therefrom after ashing, and clean particles from the substrate (e.g., by washing) prior to introducing the substrate into a metal etch reactor for the actual etching of the underlying metal layer.
Ash-type processes and/or bombardment-type processes may also be employed in the prior art to break through the organic-based ARC layer, e.g., ARC layer 110 of FIG. 3, prior to performing the main etch. The use of ash-type processes and/or bombardment-type processes for this purpose involve disadvantages as well, e.g., introducing contamination into the metal etch chamber, negatively affecting etch uniformity, reducing substrate throughput and/or increasing reactor chamber maintenance.
In view of the foregoing, there are desired improved methods and apparatus for efficiently removing photoresist mask defects on a substrate and/or etching through an organic-based antireflective coating layer.